Xilinx ISE ERROR :place:1018解決方法
狀況： 出現以下錯誤 ERROR :place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / 原文的解決方法： ERROR:Place:1018 - A clock IOB / clock component pair have been found that arenot placed at an optimal clock IOB / The IO component is placed at site . This will not allow the use of the fast path between the IO and theClock buffer. If this sub optimal condition is acceptable for this design,you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demotethis message to a WARNING and allow your design to continue. However, the useof this override is highly discouraged as it may lead to very poor timingresults. It is recommended that this error condition be corrected in thedesign. A list of all the COMP.PINs used in this clock placement rule islisted below. These examples can be used directly in the .ucf file tooverride this clock rule. 意思是： 因為rxclk是clk訊號，必須放在有CLK腳位的PIN上， 但是使用者放在B11，一個非GCLK的PIN腳，所以出錯， 解決方法，一個是重新定義在GCLK上， 一個是告訴合成器，你願意放棄效能來完成...